A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (SDC) Design

Watermarking is the process that embeds data called a watermark, tag or label into a multimedia object, such as images, video or text for their copyright protection. According to human perception, the digital watermarks can either be visible or invisible. A visible watermark is a secondary translucent image overlaid into the primary image and appears visible to a viewer on a careful inspection. The invisible watermark is embedded in such a way that the modifications made to the pixel value is perceptually not noticed and it can be recovered only with an appropriate decoding mechanism. In this paper, we present a new VLSI architecture for implementing two visible digital image watermarking schemes. The proposed architecture is designed aiming at easy integration into any existing digital camera framework. To our knowledge, this is the first VLSI architecture for implementing visible watermarking schemes. A prototype chip consisting of 28469 gates is implemented using 0.35μ technology, which consumes 6.9mW power while operating at 292MHz.